The present invention relates generally to circuits used in VLSI integrated circuits, and, more particularly to a dynamic NOR gate with a large number of inputs.
Dynamic logic gates are often used in the design of logic circuits that require high performance and minimal size. Dynamic logic gates are much faster than static logic gates, but suffer from increased noise and susceptibility from fabrication process variation. Essentially, a dynamic logic gate is a circuit which requires a periodic electrical pre-charge, or refresh, such as with a dynamic random access memory (DRAM), in order to maintain and properly perform its intended logic function. Once the electrical precharge on the dynamic logic gate has been discharged, the dynamic logic gate can perform no other logic functions until subsequently precharged.
One such dynamic logic circuit performs a logical NOR function on a large number of inputs, often eight or more. This may be called a xe2x80x9cwide NORxe2x80x9d gate. To perform this function, each of a large number of input lines are each connected to a single one of the gates of an equal number of input pulldown field-effect-transistors (FETs). The drains of each of these input FETs are all connected to a common, precharged, node. The precharged node is also connected to a transparent latch circuit known as a xe2x80x9czero catcherxe2x80x9d. In operation, if any of the input lines turns on any of the input FETs, it discharges the precharged node. This discharged state trips the zero catcher causing the output of the zero catcher to change state.
Unfortunately, as FET geometry""s shrink, leakage currents increase. Leakage currents are also a greater problem when the circuits are fabricated using silicon-on-insulator (SOI) processes. These increased leakage currents increase the size of precharge FETs and holder FETs. This may decrease the speed of the overall wide NOR circuit. Accordingly, there is a need in the art for an improved dynamic wide NOR gate.
The invention provides a wide NOR gate with improved precharge node capacitance and leakage. This improves speed for many applications. Two precharge nodes are used instead of one. During the evaluate phase of the dynamic gate, the state of the two precharge nodes may be changed by a number of pulldown FETs. The state of these two precharge nodes are combined by a logic function that is enabled during the evaluate phase of the gate to produce a signal that is latched to produce the wide NOR gate output. This latched signal is also used to provide feedback to the precharge nodes to keep them from discharging due to parasitic effects such as the leakage current. Accordingly, for the same number of input lines, each pulldown FET has to discharge approximately half the capacitance when compared to a single precharge node circuit. Also, either the number of pulldown FETs may be increased, or the size of the pulldown FETs decreased while maintaining approximately the same speed of operation.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.